In this work, we demonstrate high-performance silicon tri-gate nanowire transistor (NW Tr.) with NW width less than 15 nm. We successfully reduced the parasitic resistance of NW Tr. by raised source/drain extensions with thin spacers with < 10 nm. Furthermore, we introduced stress memorization technique (SMT) to NW Tr. And much larger mobility increase is obtained in NW Tr. than in planar Tr. The threshold voltage variability of NW Tr. is studied and the threshold voltage variability in NW Tr. is reduced compared to planar SOI Tr. due to gate grain alignment. The performance of NW Tr. CMOS circuits under the low voltage operation is investigated by using the Spice model parameters extracted from the measurement data. The operation voltage of NW CMOS inverter is reduced smaller than that of bulk CMOS due to the ideal sub-threshold slope. NW Tr. is highly promising for the ultra-low power and high-performance LSI applications.